1. Field of Invention
The present invention relates generally to the field of computerized devices, data networks and buses. More particularly, in one exemplary aspect, the present invention is directed to efficiently servicing devices of a data network.
2. Description of Related Technology
In a typical network, software processes running on a host device typically have the responsibility of managing communication between devices. In the exemplary context of serialized bus protocols, specifically the Universal Serial Bus (USB) protocol, the software responsible for much of the management functions running on a typical USB Host is known as the USB Host Controller Driver (HCD). The HCD has the responsibility for managing the workload for a USB Host Controller (HC) hardware chip that is in communication with other USB devices. The HCD manages the workload by creating a listing of so-called Queue Heads (QH), which describes the work to be done for each logical channel or “pipe”.
The various logical channels or pipes are organized into one of two different types, depending on the type of data that is to be transferred, and include: (1) stream pipes; and (2) message pipes. Stream data has no USB-defined structure, while message data does. One mandatory message pipe, known as the Default Control Pipe, always exists once a device is powered, in order to provide access to the device's configuration, status, and control information.
Each QH associated with a given pipe is created in a location in memory (e.g., in RAM) which is typically “shared”, meaning that it can be accessed either by the HCD executing on the main processor, or by the HC hardware device. As every USB device contains a Default Control Pipe, there is at least one QH for every device attached to the USB (this QH is referred to as the Control Endpoint QH). Most devices have one or more additional QHs within this shared memory space. Accordingly, each QH within a network enables software communication with one or more USB devices.
In an effort to be “fair” to every QH present on the network, the HC will take the time to examine the memory space of each of the QHs in e.g., a round robin fashion, in order to determine if the QH should be serviced. This examination of the memory space is performed even if a particular device is idle, or has nothing to communicate over a given QH. Unfortunately, examining a QH in memory takes time, which can result in missed work opportunities on those QHs which actually are “active”. This inefficiency is particularly exacerbated in situations where the number of inactive QHs significantly outnumber the active QHs. Additionally, examining an inactive QH may result in more energy being used than would otherwise be necessary, by preventing the processor from going into lower power states. This is particularly problematic for battery powered central processing units (CPUs).
Accordingly, there exists a need to improve upon the inefficiencies associated with these prior art approaches. What is needed are methods and apparatus for reducing bus activity (i.e., unnecessary activity) in order to preserve power in both the host and the client, and also to free-up available bus bandwidth for useful operations. At the same time, such methods and apparatus ideally should not significantly impede bus performance due to e.g., latencies associated with introducing unnecessary bus operations.